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1/18 ? semiconductor msm518205 description the msm518205 is a 4,194,304-word 2-bit dynamic ram fabricated in oki's silicon-gate cmos technology. the msm518205 achieves high integration, high-speed operation, and low-power consumption because oki manufactures the device in a quadruple-layer polysilicon/double-layer metal cmos process. the msm518205 is available in a 26/24-pin plastic soj or 26/24-pin plastic tsop. features ? 4,194,304-word 2-bit configuration ? single 5 v power supply, 10% tolerance ? input : ttl compatible, low input capacitance ? output : ttl compatible, 3-state ? refresh : 4096 cycles/64 ms ? fast page mode with edo, read modify write capability ? cas before ras refresh, hidden refresh, ras -only refresh capability ? multi-bit test mode capability ? package options: 26/24-pin 300 mil plastic soj (soj26/24-p-300-1.27) (product : msm518205-xxsj) 26/24-pin 300 mil plastic tsop (tsopii26/24-p-300-1.27-k) (product : msm518205-xxts-k) xx indicates speed rank. product family ? semiconductor msm518205 4,194,304-word 2-bit dynamic ram : fast page mode type with edo msm518205-70 70 ns 130 ns 150 ns 358 mw 330 mw family access time (max.) cycle time (min.) standby (max.) power dissipation msm518205-80 t rac 80 ns 35 ns t aa 40 ns 20 ns t cac 20 ns 20 ns t oea 20 ns msm518205-60 60 ns 110 ns 385 mw 30 ns 15 ns 15 ns operating (max.) 5.5 mw e2g0030-17-41 this version: jan. 1998 previous version: may 1997
2/18 ? semiconductor msm518205 pin configuration (top view) note : the same power supply voltage must be provided to every v cc pin, and the same gnd voltage level must be provided to every v ss pin. 26/24-pin plastic soj 26/24-pin plastic tsop (k type) pin name function a0 - a9, address input ras row address strobe cas1 , cas2 column address strobe dq1, dq2 data input/data output oe output enable we write enable v cc power supply (5 v) nc no connection a10r, a11r 3 4 5 9 10 11 12 13 dq2 a0 a1 a2 a3 v cc 24 23 22 18 17 16 15 14 cas1 a7 a6 a5 a4 v ss 2 dq1 25 nc 1 v cc 26 v ss 3 4 5 9 10 11 12 13 24 23 22 18 17 16 15 14 2 25 1 26 6 a11r 21 a9 21 8 a10r 19 a8 19 6 8 dq2 a0 a1 a2 a3 v cc dq1 v cc a11r a10r cas1 a7 a6 a5 a4 v ss nc v ss a9 a8 we cas2 we cas2 ras oe ras oe v ss ground (0 v)
3/18 ? semiconductor msm518205 block diagram timing generator ras cas1 cas2 timing generator internal address counter row address buffers v cc v ss on chip v bb generator row de- coders word drivers memory cells refresh control clock sense amplifiers column decoders write clock generator i/o selector output buffers we oe 2 dq1, dq2 2 2 2 2 2 input buffers 2 10 a0 - a9 12 10 10 2 a10r, a11r column address buffers function table function mode ras h l input pin cas1 * h l cas2 h we h h h l l oe l l l h l l l l l h l l h l l h l * * * * * h dq1 read dq2 read dq1, dq2 read refresh standby dq1 write dq pin dq1 high-z high-z d out d in dq2 high-z high-z high-z d out don't care high-z d out d out don't care d in dq2 write l lll h d in d in dq1, dq2 write h lll h high-z high-z h *: "h" or "l"
4/18 ? semiconductor msm518205 electrical characteristics absolute maximum ratings recommended operating conditions capacitance *: ta = 25 c voltage on any pin relative to v ss short circuit output current power dissipation operating temperature storage temperature v t symbol i os p d * t opr t stg C1.0 to 7.0 50 1 0 to 70 C55 to 150 rating ma w c c parameter v unit power supply voltage input high voltage input low voltage v cc symbol v ss v ih v il 5.0 0 typ. parameter 4.5 0 2.4 C1.0 min. 5.5 0 6.5 0.8 max. (ta = 0c to 70c) v unit v v v input capacitance (a0 - a9, a10r, a11r) input capacitance output capacitance (dq1, dq2) c in1 symbol c in2 c i/o 6 7 10 max. pf unit pf pf parameter (v cc = 5 v 10%, ta = 25c, f = 1 mhz) typ. ( ras , cas1 , cas2 , we , oe )
5/18 ? semiconductor msm518205 dc characteristics notes : 1. i cc max. is specified as i cc for output open condition. 2. the address can be changed once or less while ras = v il . 3. the address can be changed once or less while cas1 , cas2 = v ih . parameter symbol condition msm518205 -60 msm518205 -70 msm518205 -80 (v cc = 5 v 10%, ta = 0c to 70c) i oh = C5.0 ma output high voltage i ol = 4.2 ma output low voltage 0 v v i 6.5 v; all other pins not input leakage current under test = 0 v dq disable output leakage current 0 v v o 5.5 v ras , cas1 , cas2 average power t rc = min. supply current (operating) ras , cas1 , cas2 = v ih power supply ras , cas1 , cas2 current (standby) ras cycling, average power cas1 , cas2 = v ih , supply current t rc = min. ( ras -only refresh) ras = v ih , power supply cas1 , cas2 = v il , current (standby) dq = enable average power cas1 , cas2 supply current ( cas before ras refresh) ras = v il , average power cas1 , cas2 cycling, supply current t hpc = min. (fast page mode) v oh v ol i li i lo i cc1 i cc2 i cc3 i cc5 i cc6 i cc7 3 v cc C0.2 v min. 2.4 0 C10 C10 max. v cc 0.4 10 10 70 2 1 70 5 70 90 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 65 2 1 65 5 65 85 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 60 2 1 60 5 60 80 unit v v m a m a ma ma ma ma ma ma note 1, 2 1 1, 2 1 1, 2 1, 3 ras cycling, cycling, before ras
6/18 ? semiconductor msm518205 ac characteristics (1/2) random read or write cycle time read modify write cycle time fast page mode cycle time fast page mode read modify write cycle time access time from ras access time from cas access time from column address access time from cas precharge cas to data output buffer turn-off delay time transition time ras precharge time ras pulse width ras pulse width (fast page mode with edo) ras hold time cas pulse width cas hold time ras to cas delay time ras to column address delay time cas to ras precharge time row address set-up time row address hold time column address set-up time column address hold time column address hold time from ras column address to ras lead time access time from oe oe to data output buffer turn-off delay time refresh period ras hold time referenced to oe ras hold time from cas precharge t rc t rwc t hpc t hprwc t rac t cac t aa t cpa t cez t t t rp t ras t rasp t rsh t cas t csh t rcd t rad t crp t asr t rah t asc t cah t ral t oea t oez t ref t roh t rhcp output low impedance time from cas t clz cas precharge time (fast page mode with edo) t cp t ar parameter msm518205 -60 msm518205 -70 msm518205 -80 (v cc = 5 v 10%, ta = 0c to 70c) note 1, 2, 3, 12, 13 symbol note 4, 5, 6 4, 5 4, 6 4, 15 7, 8 17 5 6 15 14 14 4 7 4 3 max. 60 15 30 35 15 50 10,000 100,000 10,000 45 30 15 15 64 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns min. 150 205 35 105 0 0 2 60 80 80 20 10 15 50 20 15 10 0 10 0 15 50 40 0 10 45 max. 80 20 40 45 15 50 10,000 100,000 10,000 60 40 20 15 64 min. 130 185 30 100 0 0 2 50 70 70 20 10 10 45 20 15 10 0 10 0 15 45 35 0 10 40 max. 70 20 35 40 15 50 10,000 100,000 10,000 50 35 20 15 64 min. 110 155 25 85 0 0 2 40 60 60 15 10 10 40 20 15 10 0 10 0 10 40 30 0 10 35 data output hold after cas low we to data output buffer turn-off delay time ras to data output buffer turn-off delay time t doh t wez t rez 7, 8 7 15 15 ns ns ns 5 0 0 15 15 5 0 0 15 15 5 0 0 oe hold time from cas (dq disable) ras to second cas delay time t cho t rscd ns ns 10 80 10 70 5 60
7/18 ? semiconductor msm518205 ac characteristics (2/2) write command pulse width write command to cas lead time write command to ras lead time data-in set-up time data-in hold time from ras cas to we delay time ras to we delay time column address to we delay time ras to cas hold time ( cas before ras ) cas active delay time from ras precharge data-in hold time write command hold time write command hold time from ras oe command hold time oe to data-in delay time write command set-up time ras to cas set-up time ( cas before ras ) we to ras precharge time ( cas before ras ) we hold time from ras ( cas before ras ) ras to we set-up time (test mode) cas precharge we delay time ras to we hold time (test mode) t wp t cwl t rwl t ds t dhr t cwd t rwd t awd t csr t chr t rpc t dh t wch t wcr t oeh t oed t wcs t wrp t wrh t wts t cpwd t wth msm518205 -60 msm518205 -70 msm518205 -80 (v cc = 5 v 10%, ta = 0c to 70c) note 1, 2, 3, 12, 13 parameter symbol ns ns ns 10 10 10 note 16 11, 14 10 10 10 14 15 14 11, 14 14 10, 14 10, 15 ns 20 min. max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit ns min. 10 20 20 0 45 50 100 65 10 20 10 15 15 50 20 20 0 70 read command set-up time read command hold time read command hold time referenced to ras t rcs t rch t rrh 14 9, 14 9 ns ns ns 0 0 0 we pulse width (dq disable) t wpe ns 10 oe command hold time oe precharge time t och t oep 10 10 10 20 10 15 15 0 40 40 85 55 10 20 10 15 10 45 15 15 0 60 0 0 0 5 10 10 ns ns 10 10 10 20 min. 10 20 20 0 50 50 110 70 10 20 10 15 15 55 20 20 0 75 0 0 0 10 10 10 10 10 max. max.
8/18 ? semiconductor msm518205 notes: 1. a start-up delay of 200 m s is required after power-up, followed by a minimum of eight initialization cycles ( ras -only refresh or cas before ras refresh) before proper device operation is achieved. 2. the ac characteristics assume t t = 5 ns. 3. v ih (min.) and v il (max.) are reference levels for measuring input timing signals. transition times (t t ) are measured between v ih and v il . 4. this parameter is measured with a load circuit equivalent to 2 ttl loads and 100 pf. 5. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then the access time is controlled by t cac . 6. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then the access time is controlled by t aa . 7. t cez (max.), t rez (max.), t wez (max.) and t oez (max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. t cez and t rez must be satisfied for open circuit condition. 9. t rch or t rrh must be satisfied for a read cycle. 10. t wcs , t cwd , t rwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. if t cwd 3 t cwd (min.) , t rwd 3 t rwd (min.), t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. these parameters are referenced to the cas leading edge in an early write cycle, and to the we leading edge in an oe control write cycle, or a read modify write cycle. 12. the test mode is initiated by performing a we and cas before ras refresh cycle. this mode is latched and remains in effect until the exit cycle is generated. in a test mode ca0 and ca1 are not used and each dq pin now accesses 4-bit locations. since all 2 dq pins are used, a total of 8 data bits can be written in parallel into the memory array. in a read cycle, if 4 data bits are equal, the dq pin will indicate a high level. if the 4 data bits are not equal, the dq pin will indicate a low level. the test mode is cleared and the memory device returned to its normal operating state by performing a ras -only refresh cycle or a cas before ras refresh cycle. 13. in a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. these parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 14. these parameters are determined by the falling edge of either cas1 or cas2 , whichever is earlier. 15. these parameters are determined by the rising edge of either cas1 or cas2 , whichever is later. 16. t cwl should be satisfied by both cas1 and cas2 . 17. t cp is determined by the time both cas1 and cas2 are high.
9/18 ? semiconductor msm518205 notes concerning cas1 and cas2 control overlap the active-low timings of cas1 and cas2 . skew between cas1 and cas2 is allowed under the following conditions: (1) the timing specification for cas1 and cas2 should be met individually. (2) different operation modes for cas1 / cas2 are not allowed (as shown below). ras cas1 cas2 we delayed write early write (3) closely separated cas1 / cas2 control is not allowed. however, when the condition (t cp t ul ) is satisfied, fast page mode can be performed. ras cas1 cas2 t ul
10/18 ? semiconductor msm518205 "h" or "l" ras cas v ih v il C C v ih v il C C dq v oh v ol C C address v ih v il C C we v ih v il C C oe v ih v il C C t rc t ras t rp t ar t crp t csh t crp t rcd t rsh t cas t rad t asr t rah t asc t cah t ral row column t rcs t rrh t rch t aa t roh t oea t cac t rac t oez t cez open t clz valid data-out t rez timing waveform read cycle write cycle (early write) "h" or "l" ras cas v ih v il C C v ih v il C C dq v ih v il C C address v ih v il C C we v ih v il C C oe v ih v il C C t rc t ras t rp t ar t crp t rcd t csh t rsh t crp t cas t rad t rah t asr t asc t cah row column t wcs t wch t wcr t dhr t ds t dh valid data-in t wp t ral open t rwl t cwl e2g0099-17-41l
11/18 ? semiconductor msm518205 read modify write cycle "h" or "l" ras cas v ih v il C C v ih v il C C dq v i/oh v i/ol C C address v ih v il C C we v ih v il C C oe v ih v il C C t rwc t ras t rp t ar t crp t csh t rcd t crp t rsh t cas t asr t rah t asc t cah row column t cwd t cwl t rwd t rwl t wp t aa t awd t oea t oed t cac t rac t oez t ds t dh t clz valid data-out valid data-in t rad t rcs t oeh
12/18 ? semiconductor msm518205 fast page mode read cycle (part-1) fast page mode read cycle (part-2) C C C C C C C C v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v oh v ol row column t crp t crp t rp t rasp t cas t csh "h" or "l" column column t rcd t cp t cas t cas t hpc t cp t cah t asc t rad t rcs t rch t rac t aa t ar t cac t clz t wez t oea valid data-out valid data-out valid data-out t rah t asr t cah t asc t cah t asc t cac t aa t doh t cez t cpa t aa t cac t rcs t wpe t rscd t rhcp e e e e e e e e v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v oh v ol row column t crp t rp t rasp t cas t csh "h" or "l" column column t rcd t cp t cas t cas t hpc t cah t asc t rad t rcs t aa t rrh t ar t cac t clz t cpa t oea valid data-out valid* data-out t rah t asr t cah t asc t cah t asc t rac valid data-out t aa t cac t doh valid* data-out t cac t rez t oez t oez t cho t och t aa t oea t oep t oep t oea * : same data, t rscd t cp t rhcp
13/18 ? semiconductor msm518205 fast page mode write cycle (early write) fast page mode read modify write cycle C C C C C C C C v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v ih v il t asr row column t crp t rp t rasp t cas t csh t rah column column t rcd t cp t cas t cas t hpc t cp t hpc t asc t cah t cah t cah t asc t asc t rad t ar "h" or "l" t dh t ds t wch valid data-in t ds t dh t ds t dh t wch t wch t rsh valid data-in valid data-in t dhr t wcs t wcs t wcs t rscd e e e e e e e e v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v i/oh v i/ol t asr row column t rasp t cwd t rah column t rcd t cp t asc t cah t cpa t asc t rad t rwd "h" or "l" valid data-out t oez t oed t ds t wp t awd t rcs t cwd t rwl t cac t awd t rac t wp t clz t dh t oeh valid data-in t oea valid data-out t oez t oed t cac t dh t oeh valid data-in t oea t clz t ds t aa t aa t rcs t cah t cpwd t hprwc t crp t ar t cwl t rscd
14/18 ? semiconductor msm518205 ras -only refresh cycle cas before ras refresh cycle f p q r s \ ] ^ k l m v ih v il ras t rp C C cas v ih v il C C v ih v il we v v "h" or "l" t rc t ras t rpc t chr t rp t rpc t cp t csr t wrp t wrh t cez t wrp open C C ol oh C C dq note: oe , address = "h" or "l" : f m n o p q r s k ] ^ _ v ih v il ras t t rp t C C cas v ih v il v ih v il C C address ras "h" or "l" rc note: we , oe = "h" or "l" t crp t rpc t asr t rah row v oh v ol C C dq t cez C C open
15/18 ? semiconductor msm518205 hidden refresh read cycle hidden refresh write cycle C C C C C C C C v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v ih v il "h" or "l" t asr row column t crp t rc t asc t rp t ras t rcd t rsh t rad t cah t rah t ral t rwl t chr t ras t rc t rp t ar t dhr t ds t wp t wch t dh valid data-in t wcr t wcs ras cas address oe v ih v il C C v ih v il C C v ih v il C C v ih v il C C "h" or "l" we v ih v il C C dq v oh v ol C C t rc t rc t ras t rp t ras t rp t ar t crp t rcd t rsh t chr t rad t asr t rah t asc t cah row column t rcs t ral t rrh t aa t roh t oea t cac t rac t clz t oez valid data-out open t cez t rez
16/18 ? semiconductor msm518205 test mode initiate cycle v ih v il ras cas v ih v il C C C C t ras "h" or "l" v oh v ol C C v ih v il C C open t rc t wth t rpc t wts t cp t csr t chr t off note: oe , address = "h" or "l" t rp we dq
17/18 ? semiconductor msm518205 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). soj26/24-p-300-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.80 typ. mirror finish
18/18 ? semiconductor msm518205 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.29 typ. tsop ii 26/24-p-300-1.27-k mirror finish

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